Exemplary embodiments relate to a method of operating a nonvolatile memory device and, more particularly, to a method of operating a nonvolatile memory device, which is capable of reducing an error of a read operation due to an increase in the width of the distribution of a threshold voltage.
A nonvolatile memory device includes a memory cell array and a page buffer.
The memory cell array includes a cell string having a number of memory cells coupled thereto in series, a source select transistor coupled to one terminal of the cell string, and a drain select transistor coupled to the other terminal of the cell string. For the cell strings, the memory cells arranged in a row across the cell strings are coupled to a corresponding word line. Here, the cell strings are coupled to bit lines by the drain select transistor. Furthermore, the cell strings are coupled to a common source line by the source select transistor. Meanwhile, the bit lines of the memory cell array are classified into even bit lines and odd bit lines. Cells coupled to the same word line constitute a page.
The page buffer may temporarily store data to be written in the memory cell array. Until the data temporarily stored in the page buffer is written/programmed into a selected memory cell of the memory cell array, a program operation and a verification operation are repeated for a certain number of times. The program operation is performed by supplying a program voltage to the selected memory cell in order to program the selected memory cell with a threshold voltage of a specific level or more. The verification operation is performed by supplying a verification voltage to the selected memory cell in order to verify whether the selected memory cell has been programmed with the threshold voltage of the specific level or more. When all the memory cells are programmed through the program and verification operations, the threshold voltages of the memory cells according to program states are distributed near the verification voltage.
To read data stored in a selected memory cell, a read operation is performed by supplying a read voltage to the selected memory cell to read a program state of the selected memory cell. During the read operation, the level of the read voltage to read the program state of the memory cell is determined by the width of threshold voltages' distribution according to the program state of the memory cell. In particular, in a nonvolatile memory device of a Multi-Level Cell (hereinafter referred to as ‘MLC’) type, the width of the distribution of threshold voltages has a great influence on the operating voltage of the memory cell as compared with a nonvolatile memory device of a Single Level Cell (hereinafter referred to as ‘SLC’) type having only two states “1” and “0”.
FIG. 1 is a diagram illustrating the distribution of threshold voltages of a nonvolatile memory device of an MLC type.
The MLC stores 2 bits, and the MLC type nonvolatile memory device has four states; ‘11’ (an erase state), ‘01’ (a first program state P1), ‘10’ (a second program state P2), and ‘00’ (a third program state P3). The MLC type nonvolatile memory device having a number of the states requires the read voltage with plural levels for reading of the respective states. Furthermore, to maintain a stable read operation of the nonvolatile memory device a read margin for each state has to be sufficiently secured. Here, the width of the distribution of the threshold voltages for each state is a factor to determine the read margin and the read voltage level. However the width of the distribution of the threshold voltages is increased because of interference phenomenon between neighboring memory cells. Since the width of the distribution of the threshold voltages is increased, it becomes difficult to set up the read voltage level and to secure the proper read margin. Accordingly, a concern is raised in that an error occurs during the read operation of the nonvolatile memory device.